Senior FPGA Engineer

The Space Dynamics Laboratory (SDL) has been developing innovative technologies and solutions for cutting-edge DoD and intelligence programs for almost six decades. Our expertise is in space and airborne IR, VIS, UV, and RF sensors, small satellite technologies, test and calibration, cybersecurity, data visualization and assurance, and ground stations.

SDL is seeking a highly skilled, experienced engineer to develop space-based FPGA firmware. The selected candidate will be involved in all aspects of payload instrumentation development, including architecture and protocol selection, control loops, algorithms, and DSP implementation in VHDL using the Xilinx Vivado development platform on the Kintex Ultrascale+.

The selected candidate must be able to work as part of larger electronics teams, internal and external to the organization, and own all aspects of their assigned block of the design from concept to integration.

·  BS degree in electrical engineering, computer science, or related field

·  Minimum of four years of experience designing, simulating, implementing, testing, debugging, and delivering FPGA-based digital electronics in VHDL or similar firmware development languages and development tools

·  Experience with FPGA debugging tools and hardware troubleshooting equipment

·  Experience in specifying, selecting, and implementing FPGA support peripherals devices

·  Experience with power management/optimization strategies

·  Familiarity with error mitigation/correction techniques

·  Demonstrated experience completing a project from requirement definition to integration and test

·  Must have or be able to obtain a DoD security clearance

·  Must be a US citizen

·  Must be able to travel domestically, up to two to three days a month

·  MS degree preferred

·  Six to ten years of relevant experience

·  Experience with in the Xilinx Vivado development environment

·  Experience developing for the Kintex Ultrascale+ FPGA

·  Experience implementing custom DSP algorithms in FPGAs

·  Experience in implementing data networks, including Ethernet, CAN Bus on high reliability design for space-borne systems

·  Experience with printed wiring assembly design rules as they relate to high-speed digital logic design concepts, static timing analysis, and the process by which timing closure is achieved in a design

SDL Benefits: SDL offers competitive salaries and benefits. As a University Affiliated Research Center (UARC), SDL also offers unique benefits, such a flexible work schedule and discounted USU tuition of 50% for employees and dependents.